Designing and implementing a fpga-based layer 2 ethernet switch

Abstract

This thesis is to analyze our methods, designs, and final results of a design of FPGA-based Layer 2 Ethernet Switch. To implement the design, we inherit and develop a new design of Layer 2 Ethernet Switch IP Core embedded on the Virtex- 6 FPGA ML605 Evaluation Kit, using primarily the Verilog Hardware Description Language, and also design several embedded programs and software applications to configure and evaluate the quality of the design. Specifically, the FPGA-based Ethernet Switch supports a maximum of 8 Ethernet Ports with bandwidth 10/100/1000 Mbps each port, several methods of transmissions such as Broadcast, Unicast, and Multicast (tagged VLAN and Ingress port Mirroring), and the automatic deletion of MAC entries in CAM Table. The measurement and evaluation results show that our Ethernet Switch passes many tests of basic functions, has a high degree of customization, is easily configurable, and has significantly lower latency compared to a particular switch on the market and very low latency in some particular cases. From collecting results, this research has shown an alternative to normal Layer 2 Ethernet Switch and provided some possible abilities to improve and develop other functions on the FPGA-based Ethernet Switches