A high precision clock duty cycle calibration design for high bandwidth die to die phy in hyper scale data centers, 5g and machine learning

Abstract

DCC circuit is designed for high-speed interfaces such as Double Data Rate (DDR) technique for Machine Learning and 5G. It corrects the distortion of clock signal in the transmission line, or due to variation of the circuit's voltage and temperature. The DCC has improved stability compared with all-analog DCC, and larger correction range, and operating frequency as compared with all-digital DCCs. The DCC is designed based on 10nm FINFET technology and uses Digital block to control Analog blocks by Finite State Machine. which made attainable the output duty cycle correction to 50 ± 0.1% over the input duty-cycle range of 40–60% for up to 2GHz. The supply voltage is from 0.675V - 0.825V and the operation voltage is -40°C to 125°C. The disadvantage of the proposed DCC is having a smaller operating frequency and correction range than all-analog DCC