FPGA implementation of open-source Central-Processing-Unit (CPU) RISC-V with hardware accelerator modules run on Linux operating system

Abstract

The growing computing needs of artificial intelligence, machine learning, IoT as well as new computing needs in different power and performance dimensions have increased overall demand and competition for custom processors, which is built for specific application needs. In addition, since legacy instruction set architectures (ISAs) have been around for decades, they are not designed to handle the latest jobs. RISC-V, an open source hardware instruction architecture, was created to solve the above problems. RISC-V is providing the flexible design and powerful customization needed to create a custom processor. In this thesis, we introduce a FPGA implementation of open-source CPU RISCV-V with hardware accelerator module. The CPU of choice is the VexRiscV, a RISC-V CPU that has been implemented completely in SpinalHDL. To solve the problem of adding new hardware accelerator module to the core, we can use the concept of plugins. The soft-cpu VexRiscV is generated with a series of Scala-scripts and can be modified by inserting or removing plugins into the scripts. We then implemented a simple algorithm to calculate the sine and cosine of an angle, thereby clarifying the design processes for the custom processor. The evaluation is mostly based on the results of debugging with Elipse, in addition an implementation including custom extensions will be loaded onto the Altera DE2 board and the results will be viewed through the terminal window