Synchronous single-port SRAM 1024x32mux4

Abstract

Static Random-Access Memory (SRAM) has become phenomenally crucial to a board spectrum of VLSI designs and applications, ranging from high-performance CPUs to low-power mobile hand-held devices. As technology scaling helps to drive density and performance, it also poses some technical challenges in designing. This thesis presents the pre-layout design for a 32kbit 6T synchronous single-port SRAM using 4-bit column multiplexer method and 28nm technology. Working with the project for 5 months, we were able to experience all steps in Pre-layout stage, from defining Specification, Floorplan to generate circuit netlist level and verify its function as well as PPA (Power – Performance – Area) over PVT (Process – Voltage – Temperature). Several sessions of this paper list out some technical issues of the design and propose their corresponding optimization method to meet various product standards. To sum up, our SRAM consists of 4 primary blocks: RWCTL, IO, RWROW and MEMORY. It can perform Read/Write action in one cycle and expect to work robustly over the temperature range from -40°C to 125°C, with supply voltage 0.9 ± 10% and corners SS, TT, FF. Despite a very basic project, since Single-Port SRAM is a very classic model in memory factory, we still take this project seriously. We see this as a very firm first step to gain basic understanding on Semiconductor Technology and Application-specific Integrated Circuit (ASIC). Furthermore, we were given a precious opportunity to manipulate with several effective technical tools that can support us in our future career, such as Synopsys, Cadence, HSPICE, Custom Sim